It is conventional in the electronic industry to encapsulate one or more semiconductor devices in a semiconductor package. These plastic packages protect a chip from environmental hazards and handling hazards and provide a method for electrically and mechanically attaching the chip to an intended device. The demands on the package design include the ability to conduct high currents without self heating, low electrical and thermal resistances, high reliability under extreme power conditions and low parasitic inductances.
Various approaches to packaging semiconductor devices have been documented in the literature as well as commercialized in order to address these design requirements. In one such design, the contact between the backside of the packaged die to the external world is made through an attachment to a highly electrically conductive leadframe using low thermal/electrical resistance solder or epoxy. Some solutions leave the backside of the die exposed.
The topside pad of the silicon die is connected to the I/O pads of the package. This is a critical part of the package design since all the current and an important percentage of the heat flux has to be conducted through it. The industry uses a variety of solutions for this, including copper strap designs, ball wirebond and ribbon wirebond designs, and copper clip designs.
Each of these designs requires at least one or more wirebonds that at least connect one or more the device terminals to an I/O of the leadframe. Wirebond reliability is a major concern with these packages. The mismatch of coefficient of thermal expansion (CTE) between materials used inside the package causes thermal cycling that provides stresses and small deformations in the wirebonds. These cycling deformations create stress and deformations as a result of the joint fatigue and can lead to wirebond failure.
Further, the bondability of wires to the pads after the reflow of the clip is also a very important issue. In most cases, the flux present in the solder paste used to attach the clip to the semiconductor chip contaminates the pads to which the wires are to be bonded. This contamination requires special chemicals for removal and still is not easily removed. The cleaning process can involve several steps, including wet cleaning, plasma cleaning and/or UV ozone cleaning, that directly impact manufacturing costs and processing time.
Further, the use of wirebonds is limited to contacts that do not require low resistance or that conduct low currents. If this is not the case, then multiple wirebonds are needed per electrical connection, which also increases cost as well as reduces reliability. There is also an intrinsic limitation on the number of wires that can be bonded to a fixed area pad, which is determined by the capabilities of the wirebond tool.
In designs where the wirebond constitutes part of the impedance matching circuit, repeatability is a major issue. Also, wirebonds can be deformed or damaged during the manufacturing process. Wirebond solutions are not, therefore, as robust as desired and the wire profiles require constant quality checks.
Still further, wirebonds between semiconductor pads and package I/Os can result in capacitively and/or inductively coupled branches, thereby reducing electrical isolation, increasing cross talk, increased noise and instability and, in general, reducing performance under high current and high frequency operation.
There remains a need for a packaging solution that reduces device architecture and process complexity and that can be easily implemented (scaled or modified) for different semiconductor die designs or multiple die assemblies (multichip modules) without significant changes or modifications to the packaging process and machinery, and also a need to do so with very low parasitic resistance, inductance and/or thermal resistance. Still further, there remains a need for such a solution that does not utilize wirebonds.